@ARTICLE{5565545, 
author={Modarressi, M. and Tavakkol, A. and Sarbazi-Azad, H.}, 
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, 
title={Application-Aware Topology Reconfiguration for On-Chip Networks}, 
year={2011}, 
month={Nov}, 
volume={19}, 
number={11}, 
pages={2010-2022}, 
keywords={multiprocessing systems;network routing;network-on-chip;power consumption;reconfigurable architectures;topology;traffic;application traffic pattern;application-aware topology reconfiguration;application-specific NoC optimization method;area complexity;chip multiprocessor;complex multicore system-on-chip;inter-router connections;network latency;network mapping;networks-on-chip Networks;power consumption;reconfigurable topology;reconflgurable architecture;Computer architecture;Network topology;Power demand;Routing;Switches;System-on-a-chip;Topology;Application-specific systems-on-chip (SoCs);multi-application-based design;networks-on-chip (NoC);performance;power consumption;reconfigurable systems}, 
doi={10.1109/TVLSI.2010.2066586}, 
ISSN={1063-8210},}